Systemverilog assertion - How do I check the stable signal after implication operator?

SystemVerilog
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10

In reply to UVM_LOVE:

Using $stable :



sequence  stable_seq ;
  $stable(idle) throughout $rose(reset)[->1] ;
endsequence

property reset_chk0_p;                                         
  @(posedge clk) $fell(reset) |-> ##[0:1] idle ##1 stable_seq ; 
endproperty

// We use ##1 stable_seq  instead of  ##0 stable_seq  as idle could have changed at same clock as $fell(reset) is True OR 1 clock after $fell(reset) is True.
// Hence $stable(idle) would be False in these 2 cases had we used  ##0 stable_seq