Systemverilog assertion - How do I check the stable signal after implication operator?

SystemVerilog
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9

In reply to ben@SystemVerilog.us:

In reply to UVM_LOVE:
That’s why we test our assertions; we may have the right concept but miss a small detail.
Apologies


$fell(reset) |-> (##[0:1] idle[*1:$] ##1 1) intersect $rose(reset)[->1];

Thanks this also work.

property reset_chk0_p;           
  @(posedge clk)                 
    $fell(reset) |-> ##[0:1] idle[*1:$] ##1 $rose(reset);
                                 
endproperty