In reply to megamind:
Code looks complex and a bit misleading. Usually, $countones(v) is used when v is a vector greater than one bit. Of course, a one-bit vector is still a vector, but the goal of an assertion is to make things clearer. What you have makes my mind spin around trying to figure it out; a lot of mental gyrations. Why not write
property p_value (i, v);
if (v) (i==1'b1) else (i == 0);
endproperty
// or even more simply
property p_value (i, v);
i==v;
endproperty
// That looks more like a property of a D flip-flop.
// We typically DO NOT WRITE Assertions FOR FLIP-FLOPS
ASRT_2 : assert property(@(posedge clk) disable iff (reset) p_value(single_bit_signal,0));
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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