System verilog : stable bus signal assertion

SystemVerilog
, ,
3

In reply to ben@SystemVerilog.us:

Thank you very much Ben.
I was thinking variable “i” in the property definition should have been replaced by the signal I am passing.

After your your answer I thought I understood and hence I tried below exercise, which actually confused me more,

module asertion_ex;
  bit clk,rst;
  bit [3:0] a;
   
  //clock generation
  always #5 clk = ~clk;
   
  //generating 'a'
  initial begin
    rst = 1;
    #10 a = 1;
    #15 a = 0;
    #25 rst = 0;
    #75 $finish;
  end
   
  ASRT_2:  assert property(@(posedge clk) disable iff (rst) p_must_static(a));

  property p_must_static (i);
    //##1 $stable(i);  //attempt_1
    $stable(i);        //attempt_2
  endproperty

endmodule

As in above example, both attempt 1 and 2 worked well and no issues or assertion reported in the log, which seems okay. However in my verification environment I see a problem! Do you have a clue on this mystery? or it depends on the signals type? like logic/reg/bit etc?

Also when I tried your solution in my verification environment it worked! but not sure if that worked perfect and not falsely passing assertions(based on the above exercise confusion).

I have another case as below, in my verification environment, actually it works well, but wanted to confirm from the GOD of assertions, does it look okay or need any modification too?

  property p_value (i, v);
    if (v) ($countones(i) > 0) else ($countones(i) == 0);
  endproperty

  ASRT_2 : assert property(@(posedge clk) disable iff (reset) p_value(single_bit_signal,0));

Here I am checking, single_bit_signal should hold 0 or 1 value, based on the value I pass in argument.

Please clarify my confusions. Thank you.