System Verilog: Sequential execution in an always block

In reply to Bhaskar44:
I suggest that you study, through 1800 or books or sites, the definition and uses of static,
automatic
variables and tasks.
In an always block, locally defined static variables exists all the time, just like variables defined in modules. Locally defined automatic variables exist throughout the lifetime of the block. Locally defined variable can only be assigned as blocking. Typically, automatic variables are used as temps in the computational process since they are disposed of at the end of the block (or task). Locally static variables are used as storage.

Since you addressed the topic of race condition, study the SystemVerilog time slot regions (see 1800’2012 4.4.3 PLI regions

So the question is really all about applications.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us