In reply to Bhaskar44:
I suggest that you study, through 1800 or books or sites, the definition and uses of static,
automatic variables and tasks.
In an always block, locally defined static variables exists all the time, just like variables defined in modules. Locally defined automatic variables exist throughout the lifetime of the block. Locally defined variable can only be assigned as blocking. Typically, automatic variables are used as temps in the computational process since they are disposed of at the end of the block (or task). Locally static variables are used as storage.
Since you addressed the topic of race condition, study the SystemVerilog time slot regions (see 1800’2012 4.4.3 PLI regions
So the question is really all about applications.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115