In reply to ben@SystemVerilog.us:
Hi Ben!
I got the clarification for my doubt, however I was wondering how using the static and automatic variables makes my code better and reliable:
For ex: I said there is a clock, but say I am monitoring events, and there are 20 events, which occur regularly, so my code would be more like this:
always @(event_t1) begin
if () begin
.....
if (a<8)
if (a<4)
....
else if (a<7)
....
if (a==6)
....
count = count+1;
end//if
end // always
And this is a behavioral code, no need for synthesis.
Currently I have this working (for most cases), but however I am afraid that my model would break because of race condition for “count”, because everytime I enter an if condition, i use the count to do something, increment, and then use the incremented count to do something - all these for each event sense!
Is there a better coding approach than the above, hence wass interested in knowing how using static and automatic would make a difference ?
Also, I have always followed a practice of no blocking assignments within a clocked block. But the above solution you have provided has a mix of both NBA and blocking. Could you also please clarify on this ?
Thanks in advance!