System Verilog Round robin arbiter assertions

SystemVerilog
,
1

Hi
I am working on Round Robin Assertion. I need Simple Round robin arbiter assertion code with test bench in working condition. For now I am working with [3:0]req and [3:0] gnt .All requests are asserted at same time but Only one gnt will come at a time after one clock delay

2

In reply to sumit@2001:
https://scholarworks.rit.edu/cgi/viewcontent.cgi?article=10982&context=theses

https://www.google.com/search?q=Round+robin+arbiter+assertion+code+site:verificationacademy.com&sca_esv=557502889&rlz=1C5GCEM_en&sxsrf=AB5stBhrB_jGXIvBgssIydnYRtCgkf1QzQ:1692215317100&sa=X&ved=2ahUKEwi4uO-m-eGAAxWzMjQIHXNyCZUQrQIoBHoECBkQBQ&biw=1536&bih=818&dpr=1

3

I tried using genvar like this

genvar i;
generate for(i=0; i<4;i++)
property rr_arbiter;
  (req[i]!=0)|=>(gnt[i] ##0(onehot(gnt)));
endproperty
assert property (@(posedge clk) rr_arbiter);
endgenerate

Now There may be syntax error but I am using this method. In this I didn’t get any error but according to wave form there should be assertion error.

That’s why I was asking RR arbiter assertion code with test bench