System verilog real variable

SystemVerilog
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1

Hi,
When running simulation with real variable. I encounter this problem:

real val;
logic x;
logic y;

assign x = y ? val :'1bz;

initial begin
#1;
 y = 0;
 val = 1.2;
 $display("Value of x: %b",x);
end

The display value is 0 ,not z as intended . If you change 1’bz to 1’b1 then it will behave correctly.

2

In reply to tri.nguyen1123:

The issue here is that if either the true or false conditional expressions are real, the resulting type is real. The value 1’bz is being converted to 0.0.

To prevent this from happening, you can write

assign x = y ? logic'(val) :' 1bz;
3

In reply to dave_59:

Thanks Dave, May i ask that in general the resulting type will be the most general type of the two operands ?

4

In reply to tri.nguyen1123:

It’s all defined in section 11.4.11 Conditional operator of the IEEE 1800-2017 SystemVerilog LRM . For numeric values, its aligned with the resulting type if you were to add the two opposing values.