System verilog randomization

Suppose I have a random variable and a set of constraints/constraint.
Is there a way where every time the randomization happens on this variable it picks a particular value in all those randomizations? Is there a way we can achieve this?

For eg: Lets say we have a rand variable as ‘A’, and the constraint is A<10. Now every time the randomization happens A could be anything between 0-9.
Is there a way where we can expect this variable A to pick a particular value every time the randomization happens?

like how we have $urandom(seed) which generates the same randomized output every time.

In reply to 100rabhh:

I do not understand what you mean by “pick a particular value every time the randomization happens”. It might help to provide a sample piece of code and what set of resulting value you are looking for.

Randomization in SystemVerilog uses a seeding strategy based on threads and objects that provides random stability. That means you should get the same randomly selected value series every time you run a simulation starting with the same initial seed. Even if you change your code, this stability is guaranteed to a certain extent based o rules that are in the LRM.