System verilog randomization: inconsistency in LRM?

In reply to dave_59:

Thank you Dave. Your insights are great as usual.
I worked on an example which going by your description should have worked. It was a little complicated as main class has other class as members and randomization fails.
I had to code a hack to proceed.
If you would like to see the example, please let me know where I can send it to you? You can probably check it in Modelsim (I only have IUS, which is not too great with constraints)