System verilog opts

SystemVerilog
1

Hello ,
I want to pass test parameters in functional verification from the command line. For that, I have to use “.opt” file. I dont have much knowledge about it. can you explain me or some links which explain System verilog opts thoroughly?? and also how to code .opt file and how can I use it??

2

In reply to Ketan Dhimmar:

Your question is not clear. If the requirement is to pass arguments from commandline you can use $test$plusargs, $value$plusargs
If the requirement is to update “parameter” then vcs had -pvalue,-parameters args which can take a file as input.(This is used at compile time not at run time)

3

In reply to Naven8:

Thanks for your reply.
Yes, I want to use $test$plusargs, $value$plusargs , but using “.opt” file which contain constraints. can you give me more idea about .opt file, I mean about structure and all.

4

In reply to Ketan Dhimmar:

Where did you hear about .opt file? I’ve never head about it before. If it is tool specific, you need to contact your simulator supplier.

5

In reply to dave_59:

I think this info you can get from your tool vendor. I don’t think run time inclusion of some file is supported(in general we compile whole design and then use the simv to run the test. Tools support .so file to be included at run time but its mostly c/cpp code).

6

In reply to Naven8:

No, I don’t think so that it is tool specific. but u know about vmm_opts?
May be, the things which I am asking about are related with it.

7

In reply to Ketan Dhimmar:

If it is related to parameter definitions you can create a compile.f file including the parameter definitions in it.
While compiling add a “-f” option followed by the file name.That may serve your purpose.

If you need further control at test level then you can include them in a config file and tune them in your testcase,that would be a better practice.

Regards,
Aswin.