System verilog interface error

SystemVerilog
1

HI,
I am facing an error when i am trying to use interface in the verification environment.
The interface declaration is as follows

interface intf(input wire clock);
logic …
endinterface

ncvlog: *W,NONAIF (/prj/femodel6/FEM_VERIF/indi_work/TARUN/uvm/WB/mem/memory_interface.sv,1|25): Non Ansi Interface port declaration seen - Not official SystemVerilog syntax - [SystemVerilog].

I am unable figure out what is the error in it.Please help me.

With regards,
Tarun

2

In reply to perumallatarun:

Looks like, this is a warning not an error.

-Vishal

3

In reply to vishal.savsani:

Thanks for correcting me Vishal. May i know why that Warning is coming ?
Is the using of wire causing a problem in it?

4

In reply to perumallatarun:
You have not shown enough code.

5

Please show full code. SystemVerilog has ANSI type of port declaration and Non-ANSI port declaration.


ANSI port declaration is as follows:
output reg [7:0] my_reg); //Defined here as an output reg
//...

Non-ANSI port declaration is as follows:

``` verilog
 my_reg); //Defined here my_reg
//...
output reg [7:0] my_reg; //redefined as an output reg

SystemVerilog allows both types of declarations. The simulator is warning about the Non-ANSI style declaration in your code. Please make sure that you don’t have any Non-ANSI declarations.