System Verilog Data Type Interchangeability between Logic and Bit

SystemVerilog
1

Hello, I have following issue:
I need to model shared memory between Emulation and Host(firware)
The API to access Emulation memory takes logic[31:0] mem_content(I can not change at this moment),
if I implement DPI-C as is,
logic[31:0] mem_content will be padded Your text to link here…, even through it is claimed the layout is compatible with C.

To get the contiguous layout behavior, I have to make use bit[31:0] mem_content_for_c,
then it involves copying large chunk of data between mem_content and mem_content_for_c
In the EDA playground, I tried the following code in SV side
task display_data(inout logic[31:0] logic_data_buf);
bit[31:0] pay_load_data;
display_data(pay_load_data); //System verilog simulator is happy with it
when I play the same trick at work,
the simulator complains as input type,
Is there any other solution to avoid the copy or large chunk of memory?
Thanks

2

In reply to MichaelSong:

Packed arrays in SystemVerilog are not directly compatible with types in C. Section H.7.4 Basic types in the IEEE 1800-2017 SystemVerilog LRM defines the compatible type mappings.

You should work with your vendor directly to discuss the most efficient way of communicating between large memories. This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues.