System verilog constraints

SystemVerilog
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1

HI ,

is there any document/article which explains what constructs you can/can not use in constraint block?
like for loop is not allowed to generate constraints. is there anything standard that has consolidated list of constructs we can use while writing constraints?

2

In reply to Blitzz0418:

Any integral expression that results in true or false, plus what’s listed in section 18.5 Constraint blocks in the IEEE 1800-2017 SystemVerilog LRM.