System verilog constraints

SystemVerilog
1

Hi:

I have a base class (as uvm_object) with couple of rand data members in it, and I am extending another class to define constraints based on couple of plusargs. Below is the example code:


class inherited_class extends base_class;
`uvm_object_utils(inherited_class)

function new (string = "inherited_class");
super.new(name);
end
endfunction

if ($test$plusargs("ext_lb")) begin        //-----------------------------------------------------------
constraint c_rule {
.....;
.....;                                       Here I want to have multiple plusargs and based on which I want different constraints
.....;
}
end                                        //-----------------------------------------------------------

endclass

When I compile this code I am getting compilation error as Syntax Error token is “if”

Could someone please guide me if I am doing anything wrong here.

Thanks,
Karma

2

In reply to Karmapanchal:

The ‘if’ statement is procedural and can’t be used outside of a function/task. If you want to use a plusarg, you will need to enable/disable the required constraint block prior to randomizing.

Edit: You can use an if statement inside of a constraint, so perhaps this is another approach.

3

In reply to cgales:

Got it. I have modified the constraint block and put it under pre_randomize function as below:
function void pre_randomize();
super.pre_randomize();
`uvm_info(get_type_name(), {“pre randomize randomize called → \n”, this.sprint}, UVM_MEDIUM)
constraint upi_ext_lbmode_rule{
if ($test$plusargs(“ext_lb”)) {

  u_upiphy_agent.loopback_mode == upiphy_agent_bcm_config::LPBK_DISABLE ;
  u_upiphy_agent.slow_mode == upiphy_agent_bcm_config::DISABLE;
  u_upiphy_agent.sim_mode == upiphy_agent_bcm_config::ENABLE;
  func_mode == UPI_X20_11P2G;
  lpbk_mode == LPBK_DISABLE;
  u_upiphy_agent.func_mode == upiphy_agent_bcm_config::UPI_X20_11P2G;
      }

}
endfunction : post_randomize

But, do you have any suggestion on this? Or any better idea to deal on this?
Thanks,
Karma

4

In reply to Karmapanchal:

The constraint block needs to be outside of the pre_randomize() block. You need to separate the two statements. You can use the $test$plusargs to set a mode which can be used in the constraint:


class inherited_class extends base_class;
`uvm_object_utils(inherited_class)
 
function new (string = "inherited_class");
super.new(name);
end
endfunction

enum {EXT_LB, ....} mode;

constraint upi_ext_lbmode_rule{
if (mode==TEST_LB) {
 loopback_mode == upiphy_agent_bcm_config::LPBK_DISABLE ;
 slow_mode == upiphy_agent_bcm_config::DISABLE;
 sim_mode == upiphy_agent_bcm_config::ENABLE;
 func_mode == UPI_X20_11P2G;
 lpbk_mode == LPBK_DISABLE;
 func_mode == upiphy_agent_bcm_config::UPI_X20_11P2G;
}
}
function void pre_randomize();
super.pre_randomize();
`uvm_info(get_type_name(), {"pre_randomize called ->\n", this.sprint}, UVM_MEDIUM)
 if ($test$plusargs("ext_lb")) mode = TEST_LB;
endfunction : pre_randomize

Remember that you can’t apply constraints to other classes. You can only constrain the variables in the class being randomized().

One thing I am not sure about is if you can use call $test$plusargs() inside the constraint itself. There are some limitations on this and I would need to test this.