System verilog constraint for transaction

SystemVerilog
,
1

Hi All,

I would like to write a constraint for the following requiement;

Let’s say, there are two random fields;
a) Number of transfers
b) packet length

num_trans:
1 => 1 transfer
4=> 4 transfer
N=> ‘N’ transfers

Packet_length =>
00 => disabled//ignore
01 => 1 packet
10 => 1 packet
11=> 2 packets
//based on $countones. so packet length can be 1 or 2 only.

Scenario_1:
num_trans = 2 and Packet_length = 2, means
2 transfers should take place and in each transfer need to send 2 packets.

Scenario_2:
num_trans = 4 and Packet_length = 1, means
4 transfers should take place and in each transfer need to send 1 packet

code I have tried

module p1;
  class transfer;
    rand bit [1:0] pkt_len;
    rand bit [2:0] num_trans;
    constraint c1{
      $countones(pkt_len)>=1;
    }
    
    constraint c2{
      foreach(num_trans[i])
        num_trans[i] == num_trans[i]*pkt_len;
    }
    
    function void post_randomize();
      //$displayb("pkt_len %b", pkt_len);
      $display("%0p", obj);
    endfunction
  endclass
 transfer obj;
  initial begin
    obj = new;
    repeat (4)
    obj.randomize();
  end
endmodule

output

'{pkt_len:'h1, num_trans:'h7}
'{pkt_len:'h3, num_trans:'h0}
'{pkt_len:'h1, num_trans:'h0}
'{pkt_len:'h1, num_trans:'h6}

The solution is incorrect. Could you please suggest the best approach?

It should looks like transaction class;
For example: 2 transfers 2 packets
T1 => P1, P2
T2=> P2,P2

Thank you,
Mahesh

2

I don’t understand the results you want. Can you show us exactly the output you expect to see? Even better would be writing directed stimulus that produces an example of the output you expect to see. The we can help you with the constraints.