System verilog constraint debugging

SystemVerilog
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1

we know that we cant use display statements inside a system verilog constraint, can any one tell me how can we debug inside a constraint. an example will be more helpful.

2

The brute force way is pulling the constraint expressions out and put them in a $display. For example, if you had

class ex;
  rand bit [2:0] A[2];
  constraint {A.sum() == 10;}
endclass

and think {3,7} should have been a solution. Then you can try those numbers

module top;
  ex h = new;
  initial begin
    h.A = {3,7};
    $display(h.A.sum());
  end
endmodule

After trying a few numbers, you will see that the sum is being truncated to 3 bits.

Isolating your code into a separate testcase is always a good strategy, but not always practical. Many tools have special constraint debugging features that you can look for by looking in your tool’s User Manual or contacting them directly for support.