System verilog code error

SystemVerilog
1

how to solve errors in code

module m(input logic a,b,c,clk,output logic x,y,z);

initial
begin
y=1'b0;
z=1'b0;
end

always_comb x=a&b;
always_latch y=a|b;
always_ff @(posedge clk)
begin
if(y)
x<=a;
@(posedge clk)
x<=x&b;
end

final
@(posedge clk)
z <= x|y;


endmodule
2

In reply to mudititm:

Hi mudititm. You are driving the x signal from two different always blocks, which is illegal. How do you want the x signal to behave?

3

In reply to mudititm:

There are many errors with your code, but no one knows what the desired behavior should be, so we cannot tell you what you should do.