System verilog bind connection for generated instance

SystemVerilog
,
1

Hi,

I want to do automatic bind connection based on parameter “IF_INST” for the interface with the module present inside generate block, please note than due to some reason, I can not bind interface directly with the “test_bind” module.

module test_bind (input wire [1:0] in_a, output reg [1:0] out_a);
  
  assign out_a = ~in_a;
endmodule

module top #(parameter INST = 2);
  
  bit [(INST*2)-1:0] temp;
  
  genvar i;
  generate
    for (i = 0; i < INST; i++) begin: INST_GEN
      test_bind t_b (.in_a(i),.out_a(temp[i*2 +: 2]));
    end
  endgenerate
  
endmodule

interface test_bind_if #(parameter IF_INST = 1) (input logic [(IF_INST*2)-1:0] if_out_a, input logic [(IF_INST*2)-1:0] if_in_a);
  
  initial begin
    $monitor("%m: if_out_a: %b, if_in_a: %b",if_out_a,if_in_a);
  end
  
endinterface

bind top test_bind_if #(.IF_INST(INST)) bind_mod_if_inst (.if_out_a({INST_GEN[1].t_b.out_a,INST_GEN[0].t_b.out_a}),.if_in_a({INST_GEN[1].t_b.in_a,INST_GEN[0].t_b.in_a}));
2

In reply to piyushpatel123:

I am not sure the binsd construct is the problem here. Realize that bind is just a shortcut for manually instantiating an instance where you do not want to modify the code. Perhaps if you show what you want the result to look like, that might help us understand your problem better.

3

In reply to dave_59:

Hi Dave,

Thank you for your reply, here is my actual requirement.

I have below DUT hierarchy.

       combine_module
            |
            |-> DUT_1_inst
            |
            |-> DUT_2_inst (which is inside generate block and it will generate N number of 
                             instance based on Parameter)

I have interface which i need to bind with “DUT_1_inst” and “DUT_2_inst” signals and some of these signals are not available in “combine_module” so i need to bind interface with “combine_module” but need to connect interface signals with “DUT_1_inst” and “DUT_2_inst”.