System verilog assertion

In reply to Madhu C:

For each attempt (1) checks across multiple clocks whereas (2) checks only for 1 clock
So (1) is a better approach.

Also consider re-writing (1) as :

$fell(valid) |-> (!error)[*1:$] intersect $rose(valid)[->1];

Note that (1) too throws assertion failure at T:65 for above stimulus
Also for (1) ‘error’ must be low on the clock tick when valid goes 1->0 , else the assertion fails.