System verilog assertion

In reply to Have_A_Doubt:

my approach is
1.A1: assert property(@(posedge clk) fell(valid) |->!error[*1:] intersect !valid [*1:$] ##1 valid) $info(“pass @%0t”,$time);
2.A2:assert property(@(posedge clk) !valid |-> !error );
which one is correct?..