System verilog assertion

In reply to Madhu C:

I am assuming the starting point of the check would be when ‘valid’ goes high->low i.e $fell(valid)
Now once ‘valid’ is low , signal ‘error’ shouldn’t be high till the time ‘valid’ goes low->high
i.e we need to check that ‘error’ is low throughout when ‘valid’ is low


 property p1;
   $fell(valid) |=> ( !error ) throughout $rose(valid)[->1]; 
 endproperty

 assert property( p1 ) $display("T:%0t Pass",$time); else $display("T:%0t Fails",$time);

Note that if error is high on the same clock that valid is re-asserted then the assertion fails !!


// Eg:
bit valid = 1;
bit clk , error ;
always #5 clk = !clk;
initial begin    
    #14; valid = 0;    
    #50 ; valid = 1; error = 1;  // Both are asserted at T:65 so SVA fails at T:65
    #2 ; $finish();
  end

If the requirement is that ‘error’ is don’t care ( 0/1 ) on the clock that ‘valid’ is re-asserted (0->1) , the solution would be to use until/s_until :


 property p2;
   $fell(valid) |=> ( !error ) until $rose(valid); // Goto repetition removed from RHS sequence 
 endproperty

 assert property( p2 ) $display("T:%0t Pass",$time); else $display("T:%0t Fails",$time);