System verilog assertion

how can i write assertion for
property read_assertiojn;
@(posedge clk) (command==1 |-> (##2 command==2 || ##5 command==4 || ##6 command==3)
endproperty

assert property(read_assertion);

there is a syntex error in the way i wrote assertion.

In reply to arshi ali:
You need the sequence ORing operator and not the logical ORing operator. Thus,


ap_cmd: assert property(@(posedge clk) command==1 |-> 
          ##2 command==2 or ##5 command==4 or ##6 command==3);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  1. VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
  2. http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
  3. “Using SVA for scoreboarding and TB designs”
    http://systemverilog.us/papers/sva4scoreboarding.pdf
  4. “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
    October 2013 | Volume 9, Issue 3 | Verification Academy
  5. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy