System verilog Assertion with throughout operation

SystemVerilog
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4

In reply to ben@SystemVerilog.us:
Hi Ben,

Thanks for the update.It is working in my case.
I am getting confusion to print Assertion pass/fail info in report summary.

Pass info is coming only once when antecedent {$rose or $fell} is asserting for the first time.
Pass Info is not coming when antecedent is true for next time .Only this is happening with pass info
But Error info is coming whenever antecedent { $rose or $fell} is true but consequent is not true.
I am writing assertion as below
property valid_assert ;
@(posedge clk_i ) disable iff (!(rst_n_i))
$rose(valid |-> ((valid_cnt <=valid_in) && (valid_cnt>0));
endproperty

  valid_assert_check : assert property (valid_assert)
 `uvm_info("QAU0:: PASS VALID ASSERT", $psprintf("Valid asserted Correctly  inp_register= %d valid_cnt=%d",valid_in,valid_cnt),UVM_HIGH)
 else
 `uvm_error("QAU0:: FAIL PASS VALID ASSERT", $psprintf("Valid asserted Correctly  inp_register= %d valid_cnt=%d",valid_in,valid_cnt))

In my simulation valid is asserting twice or thrice. In report summary it print it is asserting only once.
[QAU0:: PASS VALID ASSERT] 1

Is there any issue in my assertion ?