System verilog Assertion with throughout operation

SystemVerilog
, ,
2

In reply to kuldeep sharma:
You need the sequential ORing instead of the logical ORing. Thus,


property almost_empty_status ;
    @(posedge u_dma_ctrl.clk_i ) disable iff (!(u_dma_ctrl.rst_n_i)) 
    $rose(u_dma_ctrl.fifo_empty_o) |->
      u_dma_ctrl.fifo_empty_o throughout (u_dma_ctrl.occ_cnt_o <=u_dma_ctrl.fifo_empty_th)[->1]
    or (u_dma_ctrl.occ_cnt_o==0))[->1];
endproperty

Ben Cohen
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