In reply to ben@SystemVerilog.us:
In reply to Saraswati:
I can easily spoonfeed you the answer, but it would be more beneficial for you if I explain the technique and then you do the research to write the code.
In SVA, within a declared property, you store the value of that signal in a local property variable. You then check in the consequent if within a region of cycles the signal value ==the local variable.
Ben systemverilog.us
Hello Ben,
Please write such an example for me. I want to do exactly what you said, but I did not use until now neither if conditions in properties nor property local variables.
An example, if it is helpfull for you to understand my need: if a 1 bit signaled toggled (let’s say from low to high, but the level reached by signal can be kept into a variable), and its high value is steady high for 8 clock cycles, it MUST be steady high another 90 clock cycles.
If example above is not clear, I have another one: if a signal changed his value, it must be steady for 30 clock cycles in that value.
Whichever of two above examples you solve, it is very beneficial for me because you will initiate me in building such type of SV Assertions.
Thanks in advance.
Alexandru