System verilog assertion to check that signal 'a' takes a value only when it has taken some other particular value before

SystemVerilog
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7

In reply to ben@SystemVerilog.us:

In reply to devil47:
I think this is what you mean

 
bit latched_a; // latched when a==d1
property p1;
@(posedge clk) latched_a && (a==d2) |-> valid;
endproperty

Hi Ben,
I meant more along these lines. Because it may be possible that a==d1 never occurred.
So, when a==d2 occurs it should make sure that a==d1 occurred in the past.


bit latched_a; //latched when a==d1

property p1;
@(posedge clk) (a==d2) |-> latched_a;
endproperty