System verilog assertion to check that signal 'a' takes a value only when it has taken some other particular value before

SystemVerilog
,
6

In reply to devil47:
I think this is what you mean

 
bit latched_a; // latched when a==d1

property p1;
@(posedge clk) latched_a && (a==d2) |-> valid;
endproperty