System verilog assertion to check that signal 'a' takes a value only when it has taken some other particular value before

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben,
In the solution you provided, it takes the assumption that if a==d1 then eventually a==d2.
But what if a was never equal to d1, then the assertion will never be checked.

I feel like it can be solved by introducing a bit valid in the testbench and then set it to 1 whenever a==d1.

property p1;
@(posedge clk) (a==d2) |-> valid;
endproperty

Let me know if I am wrong somewhere.
Thanks,