In reply to Saraswati:
You need to write the assertion in a forward-looking manner, meaning that if some condition (a sequence)now then a future condition (a property or sequence) later. DO this instead of thinking of "if a condition now, then a previous condition must have occurred.
bit clk, a, b;
int d1=1, d2=2;
// signal 'a' takes a value ''d2' only when it has already had the value
// ''d1' anytime before, during the simulation.
// Assertion wirtten in a more generic manner for the values of "a"
// If you want specific values, you can use the "let"
// let d1=1; let d2=2; // no not declare d1 and d1 as variables
ap_d1d2: assert property(@ (posedge clk)
a==d1 |=> strong(##[1:$] a==d2));
// or the following
ap_d1d2_b: assert property(@ (posedge clk)
a==d1 |=> strong(a==d2[->1]));
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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