System verilog assertion to check that signal 'a' takes a value only when it has taken some other particular value before

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Hi Ben,
I think you didn’t get my request correctly.
I will elaborate by giving an example :

signal = {0,1,3,8,9,2,…}

Now, I want to check that if this signal takes the value of 2, then, sometime before(no fixed time, so “0:$”) it has had the value of 1 as well.

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In your previous answer it isn’t clear to me as to how do you store the value of the signal (in this case 1) without using an ‘if condition’ ?

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Just on the side-lines, I used a checker to solve the problem :

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bit valid_signal = 'b0;

always @(*) begin
if (signal == 'd1)
begin
valid_signal = 'b1;
end

  if (signal == 'd2)
     begin
        ASSERT_RXOVER_MSG_AFTER_START_MSG: assert (valid_signal  == 'b1);
        
     end

end
/////////////////////

This works fine, but still I would like to know the alternative in SVA.

Thanks a lot!