System verilog assertion to check that signal 'a' takes a value only when it has taken some other particular value before

SystemVerilog
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In reply to Saraswati:

I can easily spoonfeed you the answer, but it would be more beneficial for you if I explain the technique and then you do the research to write the code.

In SVA, within a declared property, you store the value of that signal in a local property variable. You then check in the consequent if within a region of cycles the signal value ==the local variable.
Ben systemverilog.us