System Verilog Array

SystemVerilog
1

Hi All ,

In one of my project i have to push the data from [255:0] dyn_arr_a to [7:0] dyn_arr_b.
Could someone help me out in doing this process.
Thanks in Advance

I have tried the below snippet but it only copies partials data

module unpack;
  initial begin //{
    bit[7:0] dyn_arr_a[];
    bit [31:0]dyn_arr_b[];
    
    dyn_arr_b=new[3];
    dyn_arr_b[0]=32'hFFFFFFFF;
    dyn_arr_b[1]=32'hAAAAAAAA;
    dyn_arr_a=new[10];
 
    for(int idx=0;idx<2;idx++) begin //{
      {>>{dyn_arr_a[idx]}}=dyn_arr_b[idx];
      $display("dyn_arr_b[%0d]=%0h",idx,dyn_arr_b[idx]);
      $display("dyn_arr_a[%0h]=%0h",idx,dyn_arr_a[idx]);
    end//}
  end//}
endmodule:unpack

output :

dyn_arr_b[0]=ffffffff
dyn_arr_a[0]=ff
dyn_arr_b[1]=aaaaaaaa
dyn_arr_a[1]=aa

Regards,
Mechanic

2

In reply to Mechanic:

You should not be using a foreach loop in the assignment.

module unpack;
  initial begin
    bit [7:0] dyn_arr_a[];
    bit [31:0]dyn_arr_b[];
    dyn_arr_b=new[3];
    dyn_arr_b[0]=32'hFFFFFFFF;
    dyn_arr_b[1]=32'hAAAAAAAA;
    dyn_arr_b[2]=32'h00000000;
    {>>{dyn_arr_a}} = dyn_arr_b;
    foreach(dyn_arr_b[idx])
      $display("dyn_arr_b[%0d]=%8h",idx,dyn_arr_b[idx]);
    foreach(dyn_arr_a[idx])
      $display("dyn_arr_a[%0d]=%2h",idx,dyn_arr_a[idx]);
  end
endmodule:unpack

If this is not want you want, you need to explain your desired output.

3

In reply to dave_59:

Thanks Dave . could you please help me out in streaming operator decode.

4

In reply to Mechanic:

https://www.amiq.com/consulting/2017/05/29/how-to-pack-data-using-systemverilog-streaming-operators/

5

Hi Dave,

Could you please help me with the below definition understanding :
In Streaming Operators
Pack : when we take a multiple variable and stream them into single variable
unpack : Stream a single variable into multiple variables

how the streaming order will work in the below examples :

class eth_pkt;
// properties declared heere
endclass
byte byte_queue_dest[$];
byte_queue_dest = {<< byte{class_source.header, class_source.len,
                                 class_source.payload, class_source.crc}};

could you please help me out how the above operation is expanded. ?
dest queue consitsts {…?}

AS PER LRM :

>> causes blocks of data to be streamed in left-to-right order, while << causes blocks of data to be streamed in right-to-left order."

Please help how to consider right /left in various data types ? eg: packed types ,unpacked types , class data type and struct data type

Thanks in Advance

6

The streaming operator really should be thought as both a pack operations followed by an unpack operation.

It starts by packing everything on the RHS into a single stream of bits from left to right index for an array, or first to last element of a struct. It doesn’t matter if the arrays or structs are packed or unpacked to begin with.

Then it starts unpacking into the LHS by taking that single stream it just created either left-to-right with >> or reverses it right-to-left with <<.