System C to SV/UVM

SystemVerilog
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1

Hi, Can anyone tell me how to change the existing test bench written in system c to SV or UVM testbench ?

2

In reply to nishanthi.g:
Hire a consultant.

3

Hello all,

So I’m looking at hooking up a SystemC model to a UVM testbench and I see that there are various options out there.

Synopsys Transaction Level Interface - seems propriety (eurgh)
Cadence UVM-ML - Donated to Accellera - last update Aug 2013
Mentor UVM Connect - Donated to Accellera - last update Sep 2012

So out of the 2 offering available on Accellera, what are the experiences of folks here and do you have any preferences? (is there one more likely to be adopted over the other going forward??)