Synthesisability of a signal which is constant

SystemVerilog
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1

I haven’t had chance to work with ASIC tools yet. So I have doubts regarding the synthesisability of a signal which is constant inside the IP. And this signal is not clocked/register. So I cannot initialise it with reset. I know initial blocks are not supported for synthesis. So I would like to know if I can get away with following options. Which of these are synthesisable in ASIC?

  1. logic [31:0] offset = 32’hA0A0A0A0 ;
  2. const logic [31:0] offset = 32’hA0A0A0A0 ;

Or is it better to use localparam or macros which are compile time constants?

2

For named constants the preference should be, in order of decreasing preference:

  • enums
  • localparams
  • macros (defines)

Enums have both types and type checking. Localparams have types but no real checking. Macros are just text substitution.

3

In reply to Mitu Raj:

I know is it a little confusing, but a const variable is not a constant; it is a write once variable. It gets initialized once at the beginning of the variable’s lifetime.

It you really want a constant, use a parameter, then it cane be used for things like declaring the width of another variable.