Hi,
I am very new to System Verilog and I am having trouble with understanding some syntax errors. May i know why I am getting this error?
Error-[SE] Syntax error
Following verilog source has syntax error :
"testbench.sv", 58: token is 'endmodule'
endmodule
^
1 error
The code:
input logic clk,
input logic rst_n,
input logic clk1,
input logic rst1_n,
output logic clkout,
output logic rstout,
output logic interrupt
);
bind sys_top sys_avmm(
.clk (uif_cru.clk[0]), // <<example>>
.rst_n (uif_cru.rst_n[0]), // <<example>>
.clk1 (uif_cru.clk[1]), // <<example>>
.rst1_n (uif_cru.rst_n[1]), // <<example>>
.clkout (uif_cru.clk_mon[2]), // <<example>>
.rstout (uif_cru.rst_mon_n[2]), // <<example>>
.interrupt (interrupt) // <<example>>
)
endmodule
module top_tb();
Hope I can get help on this. Thank you.