Syntax error while trying to use function name as array

SystemVerilog
, , ,
1

Hello!

Can you tell me about the syntax error in the below code?

function bit [3:0] array_dup [10] (int i, int j);
	
		for (i = 0; i < 5; i++) 
			
				begin
			
					array_dup [i] = i;
					
					$display("a[%0d] = %0d",i,array_dup[i]); 

				end	
			
			j = 9;
			
			for (i = 5; i <= 9; i++) 
			
				begin
				
					array_dup[i] = j;
				
					$display("a[%0d] = %0d",i,j);
				
					j--;
		
				end 
	
	endfunction

The syntax error: Error: (vlog-13069) array_elements.sv(47): near “[”: syntax error, unexpected ‘[’, expecting ‘;’ or ‘(’.

I’m trying to call this function into constraint.

2

In reply to Shashank Gurijala:

https://verificationacademy.com/forums/systemverilog/could-sv-functio-return-multidimensional-arrays#reply-103328

3

In reply to dave_59:

Hi Dave!

How to modify the code below:

 

class packet;

	rand typedef bit [3:0] elements;
	
	rand typedef elements array[10];
	
	rand int i,j;
	
	function elements array_dup (int i, int j);
	
		for (i = 0; i < 5; i++) 
			
				begin
			
					array_dup [i] = i;
					
					$display("a[%0d] = %0d",i,array_dup[i]); 

				end	
			
			j = 9;
			
			for (i = 5; i <= 9; i++) 
			
				begin
				
					array_dup[i] = j;
				
					$display("a[%0d] = %0d",i,j);
				
					j--;
		
				end 
	
	endfunction
	
	constraint c {elements array == array_dup(i,j);}
	
endclass


module array_elements;

	initial 
	
		begin
		
			packet pkt;
			
			pkt.randomize;
			
		end
		
endmodule