Syntax Error -- uvm_sequence_item

UVM
1

I tried to compile the below code in vcs 2011.03-SP1.

`include “uvm_pkg.sv”
class wb_packet extends uvm_sequence_item;

rand  logic  [3:0]     address1;
rand  logic  [31:0]   data1;
rand  bit    [1:0]     cntrl;
rand  bit                rx_negedge1;
rand  bit                wait_en;

function new(string name = “wb_packet”);
`uvm_object_utils(wb_packet)
endclass : wb_packet

I get the compilation error as below

Error-[SE] Syntax error
Following verilog source has syntax error :
“…/testbench/wb_packet.sv”, 5: token is ‘uvm_sequence_item’
class wb_packet extends uvm_sequence_item;

I hope the base class library is not compiled.
Can you please help me to solve this error?

My VCS run command is as below

vcs +incdir+$UVM_HOME +incdir+$UVM_HOME/src +incdir+$UVM_HOME/src/dpi -o ./top_verilog -full64 +vcs+lic+wait +v2k -sverilog -I +cli+4 -ucli -M -f sim.fl -l compile.log

$UVM_HOME → /home/synopsys/vcs/2011.03-SP1/etc/uvm-1.1
sim.fl → This file has the list of files to be compiled.

2

use
import uvm_pkg::*;
'include “uvm_macros.svh”

3

You can use “-ntb_opts uvm” switch with VCS command line.
also try import the package rather than including.
ex: import uvm_pkg::*;