Syntax error in assertion

SystemVerilog
, ,
1

I have an assertion that look something like this


module tb;
.
.
.
generate
property clk_req_up;
 @(clk) disable iff (~out_of_reset) req |-> ##[1:5] ack;
endproperty
clk_req_up_assert: assert property (clk_req_up) else $error("clk_req_up: assertion failed");
endgenerate
.
.
.

I am getting compilation error like this:
System verilog keyword ‘assert’ is not expected to be used in this context.

Anything goes wrong here?

2

This code compiles fine for me in Questa (declaring all variables as
bit or
wire and adding
endmodule).

Usually when perfectly legal looking code does not compile, it is a problem with the code that comes before it.

Or it could be a problem with the version of the tool that you are using. If that is the case, you will need to contact your vendor.