Synchronization of two different interfaces with two different clock domains in predictor

UVM
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6

In reply to run2prem:

Hi,
thanks for your answer. I cannot plug the monitor to the intern logic of the DUT because the DUT has already disolved the protocol inside in different state machines and registers. It is difficult to have a perfect match of the protocol after these pipeline stages. I agree that would be good if i can match perfectly the interface with the pipelines, but it is not the case. :(

Thanks!!!
Best regards,
JA