Hi JA,
I see your monitor is plugged on an interface which gives too early information for your predictor. I understand the logic you like to predict is little deep down the RTL after some pipeline stages. I think its better to plug your monitor at that level i.e. interface (say Interface_A_int) close to the logic your like to predict. You will be lucky if your Interface_A and Interface_A_int exhibits a one-to-one mapping behavior so that you can reuse your monitor as such.
Alternate approach is to totally avoid modeling such time sensitive things (as it has its own maintenance effort) and accomplish verification using extensive SVAs. We dont need to model/predict always in a class container :-)
These are my kind suggestions.
Thanks,
Prem