In reply to DoDo_Drx:
The problem is you overrode the c_addr_default constraint in your derived class (BTW, see this post about the improper use of the work “child”), but when you that constraint off, the base c_addr_default remains active.
SystemVerilog does not give you an easy way to turn off both constraints. You need to provide a method in the base class to do it, or you need to assign seq to a base variable type, and access the constraint_mode from the base class variable.
An easier way to do this is provide another variable that holds the default addr value, and override the value prior to calling randomize.
class Base_seq xtends uvm_seq;
rand bit[31:0] addr;
bit [31:0] addr_default = 0;
constraint c_addr_default {
addr == addr_default;
}
enclass
class derived_seq xtends Base_seq;
function new();
super.new();
addr_default = 32'h0000_000F;
endclass
class test xtends Base_Test
derived_seq seq;
virtual task run_phase(uvm_run_phase);
super.run_phase(phase);
seq = derived_seq::type_id::create("seq");
..
seq.addr_default = 32'h 0000_FFFF;
if(!seq.randomize();
begin
`uvm_fatal("Randomization Failure")
end
endtask