Swap bit

SystemVerilog
,
2

In reply to Davebhai:

I used the below function. I haven’t tried streaming operators. We could use constraints as well; but I haven’t tried it yet.


// Code your testbench here
// or browse Examples
module test();
  
  int a = 32'h2431_6578;
  int b;
  
  initial begin
    b = sort_64bit(a);
    $display("a=%0h",a);
    $display("b=%0h",b);
    
  end
  
  
  
  function int sort_64bit(input int l_input);
    bit [3:0] temp[$];
    
    foreach(l_input[i]) begin
      if((i%4)==0) temp.push_back(l_input[i+:4]);
    end
    
    temp.sort();
    temp.reverse();

    
    foreach(temp[i]) begin
      sort_64bit[(i*4)+:4] = temp[i];
    end
    
  endfunction
 
endmodule