SVA with multiple clocks

SystemVerilog
,
4

In reply to mohabhat:

For multiclocking you can only use ##0 or ##1 to switch the clocks.
Thus, this is illegal
@(posedge clk0) x ##2 @(posedge clk1) y;

(9) - EDA Playground // is OK

property diff_clocks_prop ;   
    @(posedge clk0) x ##1 @(posedge clk1) y;  // line 15 
  endproperty
  assert property ( diff_clocks_prop );

Ben