SVA with multiple clocks

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Hi Sir ,
As the above quote specifically says "sequence operands " , it makes sense that the following is illegal :


 sequence diff_clocks_seq ;   
   @(posedge clk0) x ##2 @(posedge clk1) y;  // Invalid operator and/or operands in multi-clock context.  
 endsequence  
  assert property ( diff_clocks_seq );

However on declaring it as property the same error exists :


 property diff_clocks_prop ;   
   @(posedge clk0) x ##2 @(posedge clk1) y;  // Invalid operator and/or operands in multi-clock context.  
 endproperty
  assert property ( diff_clocks_prop );

This means that 1800: 16.13.1 is applicable to property expressions as well as sequence expressions.

I am still unclear on why is it that in my initial code , declaring ‘multiclocks’ as a property is legal whereas as a sequence it’s illegal ?