In reply to ben@SystemVerilog.us:
Hi ben , Thanks for the explanation.
I didn’t get the second point. As I think $rose() is posedge kind of thing. In your example :-
$rose(a_4bitbus) where a_4bitbus is a 4 bit signal.SO do you mean that anyvalue other than 4’b0000 will satisfy $rose , I mean $rose will take the 4bit bus as single entity and be true , a_4bitbus is changed from 0 to a non zero value.
One more thing : for this four bit bus if value changes from 4’b1100 to 4’b1000 will $rose work here as it is going from value 12 to 8.Please clarify this “a_4bitbus used with $rose”
As you have provided :- $changed(a) |-> b==$past(b,1). But according to this assertion .It implies that whenever a changes(at some ref. clock) , “b” should be 1 one clock cycle before.
But my use case is signal “a” is just a one cycle(of ref clock) delayed version of “b” and nothing else.