Hi,
Please have a look at this code.
assert property( @(posedge CLK) disable iff (!NRST)
$changed(OUT1) ##0 !SYNC1
|-> ##59 $changed(OUT2) ##0 !SYNC2
$display("sync ok"); else $display("sync NOT ok");
Basically, I want to check if OUT2 toggles exactly 59 clocks after OUT1 toggles.
However, at the first clock, the antecedent “$changed(OUT1) ##0 !SYNC1” becomes true although OUT1 does not toggle. Therefore, the assertion fails.
Appreciate your assistance!
In reply to sonofthesand:
use a ##1 as the first delay, basically a shift in when the goal of the assertion starts
assert property( @(posedge CLK) disable iff (!NRST)
##1 $changed(OUT1) ##0 !SYNC1
|-> ##59 $changed(OUT2) ##0 !SYNC2
$display("sync ok"); else $display("sync NOT ok");
Ben systemverilog.Us
In reply to ben@SystemVerilog.us:
Thank you for the prompt reply.
I have tried this method but now it gives a message towards end of simulation. Something like that Started at XXXX but not finished
In reply to sonofthesand:
In reply to ben@SystemVerilog.us:
Thank you for the prompt reply.
I have tried this method but now it gives a message towards end of simulation. Something like that Started at XXXX but not finished
This message is optionally provided by your simulation tool, but it is not a required to do so. From 1800 "
If the strong or weak operator is omitted, then the evaluation of the sequence_expr (interpreted as a property e.g., consequent) depends on the assertion statement in which it is used. If the assertion statement is assert property or assume property, then the sequence_expr is evaluated as weak(sequence_expr). Otherwise, the sequence_expr is evaluated as strong(sequence_expr).
A guideline that I provide in my SVA book "Qualify as strong properties that are sequences and have range delays or consecutive repetition operators (e.g., [*, [->, [= ) and are consequents in an assertion. This is important_when it is necessary to qualify an assertion as a failure if the consequent never terminates at the end of simulation._
In an assertion, a weak property is not required to finish.
Thus, your warning by the simulation tool is OK, but it is not a failure. If you want to see a failure at the end of simulation if the consequent did not finish, then do the following:
ap_out1_out2: assert property( @(posedge CLK) disable iff (!NRST)
##1 $changed(OUT1) ##0 !SYNC1
|-> strong(##59 $changed(OUT2) ##0 !SYNC2))
$display("sync ok"); else $display("sync NOT ok");
BTW, add labels to your assertions.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us