SVA to check sum() of 2 Unpacked Arrays

SystemVerilog
,
1

Hi,
I am trying a SVA to check that sum() of 2 unpacked array is the same on each posedge : edalink
However, I observe that the code doesn’t work on many of the EDA tools.
Since expression in an assertion must be a boolean expression ( ‘==’ returns 1’b0/1’b1 ), I believe the code should be legal

2

In reply to MICRO_91:
Can you change the property to

 
  property sum_check;
    @(posedge clk) 
    a.sum() == b.sum();
  endproperty
3

In reply to Someshg:

Refer LRM Section 7.12.3 Array reduction methods

‘with’ expression is required to calculate the actual sum of elements.

4

In reply to MICRO_91:

Looks like you have run into tool specific problems.

This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please contact your tool vendor directly for support.

5

In reply to dave_59:

Hi Dave,
I just wanted to confirm whether my understanding is correct.
As sum() returns an integer, the equality operator ‘==’ basically compares 2 integers.
As the final result would be either 1’b0/1’b1 the code in itself is legal right ?

6

In reply to MICRO_91:

Should be legal.