In reply to gulkotwar.aditya:
Sorry, but the above assertion makes no sense, with or without the delayed clock.
Comments:
- @(posedege clk) (sig_1 === 0) ##1 (sig_1 === 1) is same as
@(posedege clk) $rose(sig_1) - Your assertion fails with the same clock throughout. All this assertion is stating is that when sig_1 rises (becomes 1), it was 1 in the previous cycle(without the clk_d); obviously, it can’t be 1 the previous cycle.
- With the dealy it may be a 1 in the previous cycle.
- Use timing checks if that is your concern
- Assertions are written in the style where
antecedent |-> current_and_or_future_expectations.
AVOID the following style:
antecedent |-> past_occurences // POOR STYLE
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