SVA to check if the signal changes on the clock edge

SystemVerilog
5

In reply to ben@SystemVerilog.us:

Thanks Ben for the explanation. Just in case if we ignore delays can this be a possible solution?


``` verilog
 
input sig1;
input clk;

wire clk_d;  // delayed version of clk
assign clk_d = #0.1 clk;  // we can delay this signal by the smallest possible value

property align_clk_sig1_pos_chk ();
  @(posedege clk) (sig_1 === 0) ##1 (sig_1 === 1) |-> $past(sig_1==1,1,1,@(posedge clk_d));
endproperty 

assert property (align_clk_sig1_pos_chk)
  else $error(“signal didn’t rose @posedge of clk”);




Regards,
Aditya